Modern mobile communication devices such as those based on fifth generation (5G) wireless networks require energy efficient wide bandwidth analog to digital converters (ADC) to support digital processing of received analog radio signals. A preferred approach for supporting flexible multimode operation as well as narrow bandwidth modes such as 2G, 3G, and narrowband LTE, is to use delta-sigma (ΔΣ) ADCs because of their ability to be implemented with low power yet high dynamic range.
It is desirable to have wideband, high dynamic range, and continuous time ΔΣ ADCs that also have a low oversampling ratio. The traditional approach for implementing ΔΣ ADCs is to use high order loop filter with low resolution quantization (1 to 4 bits). However, this leads to high power consumption in the loop filter and high sensitivity to excess loop delay, variations in temperature, and variability in the manufacturing processes. Alternatively, if an energy efficient implementation of a higher resolution quantizer (such as six bits or more) is found, a lower order loop filter can be realized resulting in lower area, lower power consumption, and reduced sensitivity to variations in environment and manufacturing process.
Once a 6 bit or higher resolution quantizer has been realized, the number of comparators can be reduced using interpolation and folding techniques. Time-based interpolation and folding techniques may also make an energy efficient and robust implementation possible with a low order loop filter and high resolution quantizer.
Thus there is a need for improved interpolating analog-to-digital converters. Accordingly, it would be desirable to provide a system that addresses at least some of the problems identified above.